Field Programmable Gate Arrays (FPGAs) typically include an array of tiles. Each tile includes a Configurable Logic Element (CLE) connectable to CLEs in other tiles through programmable interconnect lines. The interconnect lines typically provide for connecting each CLE to each other CLE. Interconnect delays on signals using these interconnect lines, even between adjacent CLEs, are typically much larger than delays on signals that remain within a single CLE. Therefore, it is desirable to implement a logic function in a single CLE whenever possible, rather than spreading out the logic into two or more CLEs.
CLEs typically include combinatorial function generators, which are often implemented as 4-input lookup tables. Some CLEs can also implement any 5-input function, and some wider functions, by selecting between the output signals of two 4-input function generators with another CLE input signal. One such CLE, implemented in the Xilinx XC4000.TM.-Series FPGAs, is described in pages 4-11 through 4-23 of the Xilinx September 1996 Data Book entitled "The Programmable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) A portion of an XC4000-Series CLE that can implement any 5-input function is shown in FIG. 1. The output signals F' and G' of the two function generators F and G can be optionally combined with a third input signal H1 in a third function generator 3H to form output signal 3H'. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) The 3H function generator can implement any function of the three input signals (256 functions), including a 2-to-1 multiplexer that can be used when a 5-input function is desired. When function generators F and G share the same four input signals (F1/G1, F2/G2, F3/G3, F4/G4) and function generator 3H is programmed to function as a 2-to-1 multiplexer, output signal 3H' can represent any function of up to five input signals (F1/G1, F2/G2, F3/G3, F4/G4, H1). When the input signals driving function generators F and G are independent, output signal 3H' can represent some functions of up to nine input signals (F1, F2, F3, F4, G1, G2, G3, G4, H1).
For example, to implement a wide AND-gate in an XC4000-Series FPGA, all the function generators F, G, 3H can be configured as AND-gates, as shown in FIG. 2A. Function generators F, G are configured as two 4-input AND-gates, while function generator 3H is configured as a 3-input AND-gate. The resulting output signal 3H' is the 9-input AND-function of input signals G1-G4, H1, and F1-F4.
Similarly, as shown in FIG. 2B, a 9-input OR-gate can be implemented by configuring all the function generators F, G, 3H as OR-gates. The resulting output signal 3H' is the 9-input OR-function of input signals G1-G4, H1, and F1-F4.
Many other 9-input functions can be implemented in an XC4000-Series CLE. These wide logic functions are made possible only by the 3-input function generator 3H. Without the third function generator, the logic functions that can be implemented in a single CLE are much more limited. However, a 3-input function generator requires a great deal more silicon to implement than a more limited function such as, for example, a 2-to-1 multiplexer. Therefore, many CLEs do not include a third function generator as a supplement to a pair of 4-input function generators.
Function generator 3H can be replaced by a 2-to-1 multiplexer, with signal H1 selecting between output signals F' and G'. Replacing function generator 3H of FIG. 1 with a 2-to-1 multiplexer reduces the number of supported functions with up to nine input signals, but still provides any function of up to five input signals and reduces the silicon area required to implement a 5-input function generator. An FPGA using two 4-input function generators and a 2-to-1 multiplexer to implement a 5-input function generator is the XC3000.TM. family of products from Xilinx, Inc. The XC3000 CLE is described in pages 4-294 through 4-295 of the Xilinx September 1996 Data Book entitled "The Programmable Logic Data Book", available from Xilinx, Inc., which pages are incorporated herein by reference.
It would be advantageous to be able to implement certain wide logic gates using only two function generators. It is therefore desirable to provide structures and methods for implementing wide logic functions such as wide AND and OR-gates in a CLE while using only two function generators.